1. Field of the Invention
This invention generally relates to a dynamic type semiconductor memory.
2. Description of the Related Art
Recently, with high integration of a semiconductor integrated circuit, development of a mass storage has been promoted. Especially, a dynamic type semiconductor memory has become utilized in various fields due to advantageousness to realization of a mass storage and a low cost per bit.
Generally, a semiconductor memory is fabricated by arranging memory cells like a matrix. (This matrix-like arrangement of the memory cells will be referred to as a memory-cell matrix). Further, when a semiconductor memory is operated, a specific one of the memory cells is first selected according to an externally given address and thereafter data is read from or written to the selected memory cell. The selection of a specific memory cell is performed by first dividing the externally given address into an address for selecting one of rows of the memory-cell matrix (hereunder referred to simply as a row address) and an address for selecting one of columns of the matrix (hereunder referred to simply as a column address) and further selecting a row of the memory-cell matrix (hereunder referred to as a word line) in accordance with a row address. Thereby, data stored in each of the memory cells on the word line is transmitted on a column of the memory-cell matrix (hereunder referred to as a bit line) connected thereto.
In case of the dynamic type semiconductor memory, since capacity of each memory cell is very small, change in electric potential of each bit line is also very small. Thus, a sense amplifier is connected to each of the bit lines. A read operation of reading data stored in a memory cell is effected by amplifying a very small change in electric potential of a corresponding bit line. Further, when data is written to a memory cell, a write operation is effected by forcedly applying data from an external circuit to a bit line, which is selected as above described, after the read operation is performed.
Incidentally, operations of reading data from and writing data to memory cells of the same row address are succeedingly effected in a relatively short time by changing a column address of a memory cell which data is read from or written to, with a word line selected.
However, in case of such a conventional dynamic type semiconductor memory, data can be written only to a memory cell of a specific address in a cycle (hereunder sometimes referred to as a write-operation cycle). It is therefore necessary for writing data to all of the memory cells to perform write operations in cycles of which the number is equal to that of all addresses (i.e., the number of row addresses multiplied by the number of column addresses). For example, in case of a conventional dynamic type semiconductor memory of which the capacity is one mega bits, write operations corresponding to 1,048,576 cycles need to be performed.
Similarly, in case where data stored in all of the memory cells is cleared (or preset), since only a memory cell corresponding to an address can be cleared (or preset) in a write-operation cycle, it is necessary to perform write operations corresponding to write-operation cycles of which the number is that of all addresses. Moreover, in case where data stored in the memory cells arranged on the same word line is cleared (or preset), it is similarly necessary to perform write operations corresponding to write-operation cycles of which the number is that of column addresses.
This is a large obstacle to an increase of an operating speed of an entire system employing the conventional dynamic type semiconductor memory.
The present invention is created to obviate the above described defect of the conventional dynamic type semiconductor memory.
It is therefore an object of the present invention to provide a dynamic type semiconductor memory which can clear (or preset) data at a high speed.